1. Field of the Invention
The present invention relates to a circuit structure and a fabricating process thereof, and more particularly, to an embedded circuit structure and a fabricating process thereof.
2. Description of Related Art
As the contact number and the contact density of an integrated circuit chip increase, the contact number and the contact density of a circuit substrate for packaging chips have to increase correspondingly. In addition to the circuit substrate for packaging the chips, along with the miniaturized and thinner electronic products, the development of the circuit substrate used on a mother board of the electronic products advances gradually toward a trend of high layout density. Therefore, the requirement of the circuit substrate with high layout density continuously increases.
Currently, a fabricating process for the circuit substrate substantially includes a laminating process and a build-up process.
The laminating process includes that required patterned circuit layers and dielectric layers are laminated into a laminated structure after the patterned circuit layers on surfaces of the dielectric layers have been completely fabricated; then, a plated through hole (PTH) process is performed for connecting the patterned circuit layers in two different levels. The build-up process includes that the patterned circuit layers are formed on a substrate sequentially, and a conductive via connected with a preceding patterned circuit layer is fabricated in the process of sequentially fabricating another patterned circuit layer next to the preceding one.
U.S. Pat. No. 5,504,992 discloses a fabricating process for a circuit board. The fabricating process includes that a photoresist pattern is formed on a thin metallic layer at one side of a thin metallic panel; next, the thin metallic layer is used as an electroplating seed layer to form a circuit pattern on portions of the thin metallic layer, which are not covered by the photoresist pattern; then, the photoresist pattern is removed. Thereafter, the aforesaid two circuit patterns are embedded into two surfaces of a same dielectric layer respectively for forming a laminated structure, and a conductive material is electroplated to an inner wall of a through hole for forming a conductive channel to connect the aforesaid two circuit patterns after the through hole is formed in the laminated structure. Finally, the thin metallic panels and the thin metallic layers are removed, and the dielectric layer, the circuit patterns embedded into the two surfaces of the dielectric layer, and the conductive channel which connects the circuit patterns remain. It should be noted that in U.S. Pat. No. 5,504,992, the thin metallic layer which serves as the electroplating seed layer is removed and does not remain between the circuit patterns and the dielectric layer after the fabricating process is completed.